Job Description

Senior Design Verification Engineer – CHI Protocol Verificatio

 Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Role: Senior Design Verification Engineer – CHI Protocol Verification
Experience: 6-12 years
Location: Europe / Hybrid / Onsite/Remote

Job Description

We are seeking a highly skilled Design Verification Engineer with strong expertise in Cache Coherent Interconnect (CHI) protocol verification to join a leading semiconductor development program. The role involves verifying complex coherent fabrics and memory subsystems for next-generation high-performance SoCs.

The ideal candidate should have hands-on experience in protocol verification, developing reusable UVM environments, and debugging complex coherency scenarios.

Key Responsibilities

• Develop and execute comprehensive verification plans for CHI-based subsystems.
• Build and maintain reusable SystemVerilog/UVM verification environments.
• Develop constrained-random test cases, assertions, scoreboards, and functional coverage.
• Verify protocol compliance across:
  • Request channel
  • Response channel
  • Snoop channel
  • Data channel
• Validate cache coherency mechanisms and transaction ordering.
• Verify atomic operations, barrier transactions, and system-level coherency scenarios.
• Debug RTL and simulation issues and work closely with design and architecture teams.
• Drive functional and code coverage closure.
• Support subsystem and SoC-level integration activities.
• Contribute to verification methodology improvements and reusable VIP development.

Required Skills

• Bachelor's or Master's degree in Electronics, Computer Engineering, or related discipline.
• 6+ years of Design Verification experience.
• Strong expertise in:
  • SystemVerilog
  • UVM
  • Assertions (SVA)
  • Functional Coverage
• Hands-on experience with CHI protocol verification.
• Good understanding of:
  • Cache coherency concepts.
  • Memory hierarchy.
  • Interconnect architectures.
  • High-performance SoC design.
• Experience in constrained-random verification methodologies.
• Familiarity with protocol checkers and scoreboarding techniques.
• Strong debugging skills.
• Experience with VCS, Xcelium, or Questa.

Preferred Skills

• Experience with coherent fabrics and memory subsystems.
• Knowledge of processor clusters and shared cache architectures.
• Exposure to high-speed interface protocols.
• Scripting experience in Python, Perl, or Shell.
• Experience with Portable Stimulus and formal verification is a plus.
• Exposure to emulation or acceleration platforms is beneficial.

Soft Skills

• Strong analytical and debugging capabilities.
• Excellent communication and collaboration skills.
• Ability to work in cross-functional and geographically distributed teams.
• Self-driven with a proactive approach to problem-solving.

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Mandatory Skills

• CHI Protocol
• SystemVerilog
• UVM
• Cache Coherency
• Assertions (SVA)
• Functional Coverage
• Protocol Verification
• SoC Verification

Good to Have

• Coherent Interconnect Verification
• Memory Subsystems
• CPU Subsystems
• NoC
• Python/Shell Scripting
• Regression and Coverage Closure