Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.
Role: FPGA Verification Engineer Experience: 6 to 8 Years Location: Remote/Anywhere from India
Job Description
We are looking for an experienced FPGA Verification Engineer with strong expertise in SystemVerilog (SV) and UVM for a remote assignment. The ideal candidate should have hands on experience in FPGA/ASIC verification environments and should be capable of independently handling verification activities from planning to closure.
Key Responsibilities
Develop and execute verification plans for FPGA based designs
Build and maintain scalable verification environments using SystemVerilog and UVM
Create reusable testbenches, sequences, scoreboards, assertions, and coverage models
Perform block level and system level verification
Debug RTL issues and work closely with FPGA design engineers for issue resolution
Develop directed and constrained random test cases
Analyze simulation results, functional coverage, and regression reports
Participate in verification reviews and technical discussions
Ensure verification closure with high quality standards
Mandatory Skills
Strong experience in SystemVerilog (SV)
Hands on expertise in UVM methodology
Good understanding of FPGA verification flow
Experience in writing assertions and coverage driven verification
Strong debugging and problem solving skills
Experience with simulation tools such as QuestaSim, VCS, Xcelium, or Riviera
Good understanding of digital design fundamentals and protocols
Preferred Skills
Experience with FPGA platforms such as Xilinx or Intel/Altera
Knowledge of scripting languages like Python, Perl, or Tcl
Exposure to protocols such as AXI, PCIe, Ethernet, SPI, I2C, UART, or DDR
Experience in regression automation and CI flows
Understanding of formal verification concepts is an added advantage
Experience Required
6 to 8 years of relevant FPGA/ASIC Verification experience
Proven experience in SV and UVM based verification projects
Education
Bachelor’s or Master’s degree in Electronics, Electrical Engineering, VLSI, Embedded Systems, or related field
Additional Information
Fully remote assignment
Immediate or early joiners preferred
Strong communication and independent working capability required
