Job Description

ASIC top Level Verification Engineer

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.

Location- Onsite Bangalore/Chennai(Hybrid)

Job Title - ASIC Top Level Verification Engineer

Experience - 5-10years

Role

SoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more.

• Preparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms.

• Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier. As input you have documents and information from interaction with various type of stakeholders.

• Participate in specification and development of software driven tests written in C.

• Debug RTL designs with help of EDA simulation tools and SW debuggers.

• But also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation

• Beside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab. In case you lack experience of some platform you are expected to develop skills for such tasks.

• Contribute to keeping tests clean in the CI regression running on our four platforms.

• Who occasionally can develop of tests involving UVM VIPs (used in some of our tests)

• Who from time to time will work with gate level simulation (GLS)

• Work with formal connectivity verification

• Compile the ASIC designs to run in HW emulators, like Siemens Veloce and Cadence Palladium

• Scripting and in developing and maintaining the TLV CI flow in projects, including visualization of results 

 

Skills

• Solid C programming skills targeting ASICs or other type of embedded software programming.

• Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs.

• 5+ years of experience in relevant roles 

Desired knowledge and experience in

• Using SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC.

Experience of multi core designs is a plus.

• GLS

• Coresight and other JTAG TAP related features

• Compiling designs for HW emulation

• Formal connectivity verification

• High speed interfaces like Ethernet, PCIe, CPRI

• ARM CPUs/cores, SMMU

• AMBA interconnect, preferably using Cadence STG or IWB

 

Preferred Skills

• XPROP

• GLS with timing, Power aware GLS

• Debugging tests running on HW Emulators and or Silicon

• Simulating and debugging tests running on SystemC/TLM platforms.

• Power aware verification (digital, not mixed signal)

• Using Formal tools for power verification

• Lab experience suitable for bring-up of ASIC Silicon prototypes