description of job
Swedium Global Services is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India.
Location: Remote from EU
Job Name: ASIC Verification Engineer – SystemVerilog/UVM with UPF
Experience: 8+ Years
We are looking for an experienced ASIC Verification Engineer with strong expertise in SystemVerilog, UVM, and UPF (Unified Power Format) to join our growing verification team.
Key Responsibilities
Develop and maintain verification environments using SystemVerilog and UVM.
Perform functional and power-aware verification for complex ASIC/SoC designs.
Implement and verify UPF-based low-power features, including power domains, isolation, retention, and power state transitions.
Develop test plans, testcases, assertions, and functional coverage.
Debug RTL and verification issues in collaboration with design and architecture teams.
Execute regressions, analyze coverage, and support verification closure.
Required Skills
8+ years of experience in ASIC/SoC Verification.
Strong hands-on experience with SystemVerilog and UVM.
Good understanding and practical experience with UPF (IEEE 1801).
Experience in assertion-based verification (SVA) and functional coverage.
Familiarity with simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Strong debugging and analytical skills.
Preferred Skills
Experience with low-power verification methodologies.
Knowledge of AMBA protocols (AXI/AHB/APB).
Exposure to scripting using Python, Tcl, or Perl is an advantage.
Education: Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.