Job Description

Senior Formal Verification Engineer

Swedium Global is the growing System Engineering and Solution Company, offers services like Semiconductor Engineering R&D Services, Embedded Systems Development, Custom Application Software Development, Web and Cloud Application Development, Testing Services, Consultancy and Outsourcing services to our clients across the globe for an onsite and offshore business model. Swedium Global is having presence in Sweden, Finland, Poland, Czech Republic and in India

Job Name- Senior Formal Verification Engineer

Location- Onsite in Sweden

Role Overview

We are looking for an experienced Formal Verification Engineer to join a technically advanced ASIC development environment

You will work with formal verification of complex digital designs, helping ensure functional correctness and identify design issues early in the development process.

We believe you have experience in:

• Formal verification of ASIC / RTL designs
• Property checking and assertion-based verification
• SystemVerilog / SystemVerilog Assertions
• Debugging complex RTL and verification results
• ASIC or SoC development environments

Experience with any of the following is considered an advantage:

• UVM-based verification
• C/C++ reference modelling
• MATLAB
• SystemC

We are looking for a mid to senior-level engineer with strong analytical skills and experience working closely with design and verification teams.